1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device for verifying whether a through silicon via (TSV) operates normally.
2. Description of the Related Art
Recent semiconductor device research has focused on increasing speed and integration degree while reducing power consumption. According to 3D stack package technology, two or more chips (or dies) may be vertically stacked. Thus, the chips or dies occupy a small space, and the integration degree is improved within the same area. A through silicon via (TSV) passes through and electrically couples the stacked chips.
A TSV may have various failure modes such as a void, which is formed when a through via is not completely filled with a conductive material, a bump contact fail, and a crack of the TSV. When the TSV has a failure, the TSV cannot perform its normal functions. Therefore, TSVs need to be tested after fabrication to ensure they are functioning properly.